This invention is in the field of integrated circuits, and is more specifically directed to serial output ports in integrated circuits.
The communication of digital data over serial interfaces continues to be a viable technique in modern integrated circuits. Serial input/output ports are especially attractive for data communication between integrated circuits in which the number of external terminals must be limited, due to form factor or power concerns. A conventional serial port requires, at a minimum, only a single data terminal and a single clock terminal. In some cases, additional terminals may be devoted for an enable signal, and perhaps also for other control signals (e.g., a read/write signal indicating the direction of data flow). In any event, serial data communications are useful when “pin” count is a significant concern.
FIG. 1a illustrates a conventional application of serial data communications. In this example, controller 2 and device 4 communicate serially over serial data line SDATA. This serial communication is bidirectional (i.e., can travel either from controller 2 to device 4 or from device 4 to controller 2), and is synchronous with a serial clock signal communicated by controller 2 to device 4 on serial clock line SCLK. The direction of data flow is controlled, in this conventional example, by the state of a first serial bit communicated by controller 2 in a serial data word; alternatively, a read/write control signal may be communicated on a separate line from controller 2 to device 4. In the example of FIG. 1a, an enable control signal is also driven by controller 2 to device 4 on enable line SDEN, so that the serial port can be disabled when not in use.
The arrangement of FIG. 1a corresponds to the known application of a controller for a hard disk drive in a computer, in which controller 2 corresponds to a hard disk drive controller, and device 4 corresponds to a servo control integrated circuit for controlling the drive to a spindle motor and a voice coil motor of a hard disk drive system. Of course, this serial communication approach is also used in other applications besides disk drive control.
It has been observed, in connection with this invention, that the timing constraints on serial data communication can be quite severe, especially in serial communication for disk drive controllers. This timing is especially severe regarding the reading of serial data by controller 2 from device 4. In the example of FIG. 1a, controller 2 reads data from data line SDATA, via a buffer, into flip-flop 5.
As is fundamental in the art, conventional flip-flops, including flip-flop 5 of FIG. 1a, include two clocked latches, each clocked on opposite edges of the same clock signal. As such, the conventional flip-flop circuit is also referred to as a master-slave flip-flop, with the input latch operating as the master latch and the output latch slaved to that input, master, latch. As will become apparent from this description of conventional serial ports include input and output shift registers constructed of a sequence of flip-flops as the shift register stages.
FIG. 1b illustrates the timing of a conventional read operation in the operation of the serial port of FIG. 1a. The leading edge of clock SCLK controls the timing of this operation in this example. At time t0, the leading edge of serial clock SCLK is generated by controller 2 and applied to device 4, in response to which the serial port of device 4 initiates the process of presenting a data bit at data line SDATA. At time t1, device 4 presents a valid data bit D0 on data line SDATA; as such, the time duration tACC between time t0 and time t1 is the access time for this read operation, and corresponds to the time required for device 4 to read data bit D0 from a register stage (as will be described below) and present the bit at data line SDATA. In this conventional arrangement of FIG. 1a, controller 2 expects to latch the data state on data line SDATA into flip-flop 5 upon the next leading edge of serial clock SCLK, which is at time t2 for data bit D0. This writing operation typically requires a “setup” time tSU at which the data state (data bit D0 in this example) is to be valid on data line SDATA prior to the edge of serial clock SCLK (time t2 in this example). This setup time allows sufficient propagation delay through the input buffer and physical conductors, so that controller 2 is assured that valid and settled data states are latched.
However, as the performance and speed of integrated circuits increase, and as the performance demands of systems such as computer hard disk drives also increase, higher data rate serial communications in implementations such as shown in FIGS. 1a and 1b are required. For example, serial clock (SCLK) rates for serial communications of on the order of 80 MHz are contemplated for state-of-the-art hard disk drive systems. For the example of this clock rate, the cycle time of serial clock SCLK will be about 13 nsec. The data setup time tSU in this instance is contemplated to be about 5 nsec according to modern technology, leaving device 4 only about 8 nsec to access and present valid data at data line SDATA.
FIG. 1c illustrates the construction of a conventional serial port 6 in device 4, such as a servo controller for a hard disk drive. As shown in FIG. 1c, serial port 6 includes an input side and an output side. On the input side, input buffer 7 has an input at a terminal connected to data line SDATA, and an output connected to the input of a first flip-flop stage 140 of a sequence of flip-flops 140 through 14n arranged as a shift register. Each of input flip-flops 14 is clocked by serial clock SCLK, and advances its contents along the shift register with each cycle of serial clock SCLK. Flip-flops 14 together present their contents in parallel, for example to load a register within device 4. In operation, therefore, input data at data line SDATA is serially clocked into flip-flops 14 over a sequence of cycles of serial clock SCLK, and present their contents in parallel to the desired register.
Conversely, on the output side of serial port 6, a sequence of flip-flops 120 through 12n are also connected in sequence as a shift register. Flip-flops 12 are each also clocked by serial clock SCLK, and advance their contents toward output buffer 9 (in the direction from flip-flop 12n toward flip-flop 120). Output buffer 9 has its input connected to the output of last flip-flop 120, and its output connected through the terminal to data line SDATA. Flip-flops 12 are also operable to receive their data in parallel, for example from a register within device 4. In operation, therefore, flip-flops 12 receive the contents of such a register, and serially output data bits of those contents in sequence, over a sequence of cycles of serial clock SCLK.
As shown in FIG. 1c, input buffer 7 and output buffer 9 also receive control signal I/O, which indicates whether input buffer 7 is to be enabled to receive data from data line SDATA or output buffer 9 is to drive data line SDATA in an output operation. Control signal I/O may be a separate control line in the serial port interface, or alternatively, as in the case of many modern disk drive control systems, control signal I/O is decoded by device 4 from a particular input bit or bits received on data line SDATA. In input mode (i.e., input buffer 7 enabled to receive serial data), output buffer 9 is placed by control signal I/O into a “tri-state”, or high impedance, mode, in which the output of output buffer 9 floats. Conversely, in output mode (i.e., output buffer 9 is enabled), input buffer 7 is disabled from responding to data driven from output buffer 9, in the conventional manner.
Referring now to FIG. 1d, the construction of a conventional one of flip-flops 12 in the conventional serial port of FIG. 1c, specifically the construction of last flip-flop 120 (having its output connected to the input of output buffer 9) will now be described, by way of further background. As shown in FIG. 1d, flip-flop 120 includes master latch 16 including a pair of inverters 16a, 16b connected in series, and slave latch 18 including a pair of inverters 18a, 18b connected in series. As shown in FIG. 1d, the input of flip-flop 120 on line IN is connected to the input of inverter 16a through switch 11, the output of inverter 16a is connected directly to the input of inverter 16b, and the output of inverter 16b is connected to the input of inverter 16a through switch 13. The output of inverter 16b is connected to the input of inverter 18a through switch 17, the output of inverter 18a is connected to the input of inverter 18b, and the output of inverter 18b is connected to the input of inverter 18a through switch 19. Switches 11 and 19 are controlled by serial clock SCLK, so as to be closed when serial clock SCLK is at a high level, and switches 13 and 17 are controlled by serial clock SCLK inverted, so as to be closed when serial clock SCLK is at a low level.
According to modern technology, inverters 16a, 16b, 18a, 18b are typically implemented by way of complementary metal-oxide-semiconductor (CMOS) inverters, and switches 11, 13, 17, 19 are typically implemented by way of conventional pass gates (typically CMOS pass gates of a p-channel MOS transistor in parallel with an n-channel MOS transistor, the gates of which receive complementary clock levels). Inverters 18a, 18b in slave latch 18 may be implemented by relative small devices (i.e., MOS devices with relatively small W/L ratios), as inverters 18a, 18b are required only to drive the input of the next CMOS stage within device 4. Output buffer 9, on the other hand, includes relatively large devices, as it must drive external data line SDATA and also the load (i.e., input impedance) of the serial port of controller 2 in this example.
In operation, the input state on line IN is written into flip-flop 120 upon a falling edge of serial clock SCLK (at time t0 of FIG. 1b), as switch 11 closes and switches 13 and 17 open. The previous state of slave latch 18, at the output of flip-flop 120 is latched into inverting buffers 18a, 18b by switch 19, which closes on the rising edge of serial clock SCLK, and this state is driven at the output of flip-flop 120 to output buffer 9. Upon the rising edge of serial clock SCLK (at time t1 of FIG. 1b), switches 11 and 19 open, and switches 13 and 17 close. With switch 13 closed, the output of inverter 16b is applied to the input of inverter 16a so that the state from input line IN is stored by inverters 16a, 16b. This stored state is then forwarded to the input of inverter 18a through closed switch 17, and propagates through inverter 18a and inverter 18b to output buffer 9. This operation of flip-flop 120 and output buffer 9 repeats with each cycle of serial clock SCLK.
It has been observed, in connection with this invention, that the propagation delay of flip-flop 120 directly and adversely affects the access time tACC and the setup time tSU.